Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask may contain a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g., comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g., an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
For the sake of simplicity, the projection system may hereinafter be referred to as the “lens”; however, this term should be broadly interpreted as encompassing various types of projection systems, including refractive optics, reflective optics, and catadioptric systems, for example. The radiation system may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, and such components may also be referred to below, collectively or singularly, as a “lens”. Further, the lithographic apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic apparatus are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
The photolithographic masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or the smallest space between two lines. Thus, the CD determines the overall size and density of the designed circuit.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). However, because of increasingly microscopic size of lithographic features and high resolution systems, slight deviation of the resulting features printed on the substrate may render the device inoperable. These deviations are typically caused by physical variations (or diffraction limited imaging) of the equipment generating the image on the substrate, illumination characteristics of the system are mask, etc.
In the current state of the art, model based optical proximity correction (“MOPC) techniques provide corrective measures to minimize this undesirable deviation. MOPC determines deviation based on a comparison of simulated images, i.e., a comparison of target image, which represents the desired image to be formed on a substrate, with a predicted image, which accounts for characteristics of the illumination system, substrate, etc. In actuality, the target and predicted images are divided in a plurality of sections.
FIG. 1 illustrates an exemplary section 10 of a target image 12 and corresponding predicted image 14 (superimposed thereon). Generally, a lithographer utilizing MOPC techniques will analyze a target image at an evaluation point A typically located at the center of the respective section 10 for determining the amount of biasing that is needed at that point. This will be repeated for a different evaluation point(s) until satisfactory results are obtained.
Software packages may be utilized to assist in the MOPC analysis. As such, the target image may be represented by a mathematical expression, from which the predicted image may be derived. Well known mathematical algorithms may be utilized for determining the deviation between the target image 12 and the predicted image 14, such as the “Newton method.” The Newton method uses an iterative algorithm to determine a root of a function representing the amount of deviation between the target image 12 and the predicted image 14. The amount of deviation may then be used to determine the amount of biasing needed to compensate for the deviation.
Equation 1 represents the Newton formula for correcting a mask edge.
                              →                      Δ            ⁢                                                  ⁢            F                          =                  Δ          ⁢                                          ⁢                      I            ⁡                          (                                                ∂                  xy                                                  ∂                  I                                            )                                                          Equation        ⁢                                  ⁢        1            FIG. 2 illustrates a plot of certain components of equation 1. Line 16 represents the intensity profile at a given evaluation point. ∂I/∂xy (designated by numeral 18) represents the slope of the feature profile at the given evaluation point. ∂I represents the deviation (i.e., error in the intensity value) between the target image and the predicted image at the given evaluation point. ΔF (not illustrated) represents the amount of bias required to shift an edge of the evaluation point to compensate for the deviation between the target image 12 and the predicted image 14. If the target image 12 and predicted image 14 were the same, the intersection between the intensity profile (line 16) and line 18 would coincide with the origin of the graph, as is illustrated in FIG. 3. In other words, ΔI would be 0.
MOPC uses either an aerial image model or a calibrated model as the predicted image. A calibrated model however considers mask properties, characteristics of the tools to create the mask, resist properties, etc, and is therefore highly accurate Disadvantages to using a calibrated model include extensive calibration, including building a mask and exposing wafers, and factoring then arbitrary imaging properties that cannot be attributed to the mask, semiconductor, or any associate property. Also, the main disadvantage to using a calibrated model is that an optimized mask must be used for calibration. If one is not used, the calibrated model likely will produce inaccurate results. Thus, industry often uses the aerial image for MOPC, because it expedites and facilitates the process as it does not rely on existing tools. However, aerial models do not factor in real life imperfections, as in the case of using a calibrated model.
Regardless of the model utilized, the inventors have found that the conventional MOPC techniques do not take into account the influence of neighboring features for a given section of a target pattern. In other words, MOPC considers only the deviation between a target image and a predicted image at a given evaluation point, and does not consider errors in intensity caused by neighboring features in a given mask pattern. As a result, deviation between the target image and a prediction image remains.